The present invention relates to a semiconductor memory employing dynamic memory cells, and more particularly to technology effectively used for the speedup and lower power consumption of a semiconductor memory having a redundancy circuit.
Although a dynamic random access memory (hereinafter referred to as DRAM) used for various types of electronic equipment has the advantage of having a high level of integration and being low in bit costs, periodical refresh is required to maintain stored information. Accordingly, the DRAM is commonly used together with a memory controller having a refresh command issuing function and is therefore unsuitable for small-scale systems such as cellular phones. As storage elements for small-scale systems, presently, a static random access memory (hereinafter simply referred to as SRAM) is primarily used. However, as portable equipment grows sophisticated, there are increasing demands for larger-capacity storage elements, so that the SRAM has become unsatisfactory in terms of costs.
A method for making it unnecessary to refresh DRAM from the outside is disclosed in Japanese Published Unexamined Patent Application No. Showa 61-71491. This method divides one cycle to two time zones so that refresh is performed in the first half thereof and a read or write operation is performed in the latter half. In this way, a refresh operation can be concealed from the outside and DRAM having low bit costs can be used like SRAM (as pseudo SRAM).
A problem of the above described prior art is that, when a read/write request comes in, if a memory is being refreshed, a read or write cannot be started until the refresh operation terminates. The coming of a read/write request cannot be anticipated in advance. As the worst case, if a read/write request comes in immediately after a refresh operation is started, access time is increased by a refresh cycle time. To minimize an increase in the access time, it is desirable to minimize a refresh cycle time.
An object of the present invention is to provide a semiconductor memory capable of reducing refresh cycle time. The above described object and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.
A typical invention of those disclosed by the present patent application is briefly described below. In a semiconductor memory which includes normal memory cells provided at predetermined intersections of plural normal word lines and plural bit lines, and redundant memory cells provided at predetermined intersections of redundant word lines and the plural bit lines, and in which a redundancy relief circuit evaluates whether each of an internal address signal for a memory operation and a refresh address signal corresponds to the address of a defective word line of the plural normal word lines, and an address selecting circuit switches the defective word line occurring in the normal word line to a redundant word line according to the evaluation result, the redundancy relief circuit evaluates whether a refresh address added by one to the refresh address signal corresponds to a defective address, and during a refresh operation, the address selecting circuit selects a normal word line or redundant word line according to the evaluation result in a preceding cycle.